Ultimate Performance Limit of Gan Vertical Power FinFET
GaN vertical power FinFETs are promising high voltage switches for the next generation of high-frequency power electronics applications. Thanks to a vertical fin channel, the device offers excellent electrostatic and threshold voltage control, eliminating the need for epitaxial regrowth or p-type doping unlike other vertical GaN power transistors. Vertical GaN FinFETs with 1200 V breakdown voltage (BV), 5 A current rating and excellent switching figure of merit have been demonstrated recently on free-standing GaN substrates. Despite promising performances from the proof-of-concept demonstration, the fundamental studies on carrier transport, electric field management and interface characteristics are absent in literature. In this work, we are exploring the carrier transport and the design-space of the electric field management structures of FinFETs under extreme operating conditions (high frequency, high electric field, high temperature) combining experiments and TCAD simulations. These studies will offer detailed understanding of the device physics and potentially push the ultimate performance limit of the vertical power FinFETs.
Figure : (Left) Cross section SEM image of a fabricated vertical power FinFET on bulk GaN substrate. (Right) Simulated electric field profile during off-state (VGS = 0V) breakdown. The peak electric field near the edge of the gate pad exceeds the critical electric field of GaN and induces device breakdown.
GaN-on-Si Vertical Power FinFET
The commercialization of GaN vertical FinFETs has been limited by the high cost ($50-$100/cm2) and small diameter (~ 2 inch) of free-standing GaN substrates. The use of GaN-on-Si wafers could reduce the substrate cost by 1000×, however the growth of the thick (~10 μm or thicker) drift layers required for kV class applications is extremely challenging on Si. Alternatively, GaN grown on engineered substrates (QST®) with a matched thermal expansion coefficient could enable low-cost vertical GaN FinFETs with thick (>10 μm) drift layers and large wafer diameters (8-12 inch). In this work, we demonstrate GaN power FinFETs on engineered substrates (6-inch wafer scale) for the first time. The device demonstrates a current density of JDS=3.8 kA/cm2 at VGS= 1.5 V and VDS= 4 V when normalized with respect to the total device area, a record for vertical and quasi-vertical MOSFETs on non-GaN substrates. The current density in each fin is higher than 30 kA/cm2 at the same bias condition. The results are very promising for large wafer scale manufacturing and commercialization of vertical GaN power FinFETs.
Figure: (Left) Schematic diagram of the quasi vertical FinFET on QST® substrate.(Right) Output characteristics of the fabricated GaN power FinFET at different gate bias. The current is normalized to total active device area. Inset shows the benchmarking of current work against the state of the art vertical GaN transistors on non-GaN substrate.
Further reading : A. Zubair, et al. "First Demonstration of GaN Vertical Power FinFETs on Engineered Substrate." 2020 Device Research Conference (DRC). IEEE, 2020.